The e Hardware Verification Language

Abstract

Includes index. This book provides a detailed coverage of the e-hardware verification language (HVL), state of the art in verification methodologies, and the use of eHVL as a facilitating verification tool in implementing a state of the art verification environment. To this end, the book provides a comprehensive description of the new concepts introduced by the e-language, e-language syntax, and its associated semantics. In addition, the book describes architectural views and requirements of verification environments (i.e. randomly generated environments, coverage driven verification environments, etc.). Verification blocks in the architectural views (i.e. Generators, Initiators, Collectors, Checkers, Monitors, Coverage Definitions, etc.) and their implementations using the eHVL are also discussed in detail in separate parts of the book. The book describes the eReuse Methodology (RM), the motivation for defining such a guideline and step-by-step instructions for building an eRM compliant eVerification Component (eVC). A complete implementation of a UART eRM compliant eVC is used as the working example for putting all topics in perspective. This book is useful for a range of users, including junior verification engineers looking to learn just enough basic concepts and related syntax to get a head start on their project, advance users looking to enhance the effectiveness and quality of a verification environment, developers working to build eVerification Components and finally as reference for looking up specific information about a verification concept and its implementation using the eHVL.