Performance Analysis of SoC and Hardware Design Flow in Medical Image Processing Using Xilinx Zed Board FPGA

Abstract

The requirement of the real-time implementation of the image processing algorithm compels FPGA adoption due to parallelism, reconfigurability, and pipelining architecture. This paper presents the coherent design of advanced edge detection algorithms using two design methodologies with FPGA: SoC design flow and hardware flow for the medical image processing purposes. Vivado HLS and Vivado IP integrator implement the SoC design flow, while system generator realizes the hardware flow. We have implemented Canny–Deriche edge detection and Laplacian of Gaussian (LoG) edge detection and practiced several brain tumor images with distinct mathematical parameters such as threshold and standard deviation. Thus, this paper aims to examine two edge detection algorithms in terms of noise reduction, edge response characteristics, and edge localization, and two design methodologies in three parameters: power consumption, resource utilization, and timing constraints. We present a real-time image processing method utilizing a pipeline structure that emphasizes medical image enhancements using this system on the Zed board SoC FPGA platform.