R-NoC: An efficient packet-switched reconfigurable networks-on-chip

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Abstract

Networks-on-Chip (NoC) architectures have been proposed to replace the classical bus and point-to-point global interconnections for the next generation of multiple-core systems-on-a-chips. However, the one-to-one (unicast) based NoC communication paradigm is not efficient for one-to-many (multicast) communication requests, and the address based packet routing method lacks the capability to arrange routing globally for overall communication performance. To address these problems, we here propose a Reconfigurable NoC (R-NoC) architecture. The novelty of the R-NoC is that a structured virtual routing path can be established through the reconfiguration of routers so that packets are delivered fast along the pre-configured routing path. Load balance for overall communication performance can be achieved through the global arrangement of routing paths. In addition, custom network topology is proposed for specific set of applications to reduce the costs on area and power. Software simulations show that the structured data path approach has a significant performance improvement on multicast comparing with the traditional multiple unicast approach. © 2012 Springer-Verlag.

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APA

Fan, H., Chen, Y. A., & Wu, Y. L. (2012). R-NoC: An efficient packet-switched reconfigurable networks-on-chip. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 7199 LNCS, pp. 365–371). https://doi.org/10.1007/978-3-642-28365-9_33

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