Dynamically reconfigurable cores

Abstract

Dynamic reconfiguration of digital circuits on FPGAs has been an area of active research for the past decade. The identification of generic classes of circuits that would benefit from being dynamically reconfigured remains a key, open problem. We report on an investigation of the application of dynamic reconfiguration to programmable, multi-function cores (PMCs). An abstract analysis of the technique is included to emphasise the generality of the methodology. Empirical results for a case study involving a universal asynchronous receiver and transmitter (UART) are presented. We show that significant improvements in area efficiency and the operating speeds of the circuits are achieved. Furthermore, the results indicate the potential for reducing the power consumption of the circuits.