Performance evaluation of an efficient 5-2 compressor for digital applications

Abstract

This paper presents an efficient performance 5-2 compressor which consumes less power. The architecture of this compressor consists of full adder, XOR’s, CGEN and MUX blocks. This architecture is mainly implemented based on Cout signals independent of Cin signals in order to reduce the carry propagation to a compressor. An efficient full adder is used to optimize the compressor architecture. In this design, an existing carry generator, XOR, MUX blocks configure with the proposed full adder circuit. The proposed design for full adder employs using pass transistor logic, which eliminates the weak logic in the circuit. This technique is mainly considerable for less power consumption. The parameters of proposed architecture is compared with other designs i.e. power-delay product, average-power, and delay. Simulations were done using HSPICE software in 130nm and 32nm technology. The simulation results show the improvement in the overall performance of the 5-2 compressor.