A highly fault detectable cache architecture for dependable computing

Abstract

Information integrity in cache memories is a fundamental requirement for dependable computing. As caches comprise much of a CPU chip area and transistor counts, they are reasonable targets for single and multiple transient faults. This paper presents: 1) a fault detection scheme for tag arrays of cache memories and 2) an architectural cache to improve dependability as well as performance. In this architecture, cache space is divided into sets of different sizes and different tag lengths. The error detection scheme and the cache architecture have been evaluated using a trace driven simulation with soft error injection and SPEC 2000 applications. The results show that error detection improvement varies between 66% and 96% as compared with the already available single parity in microprocessors. © Springer-Verlag 2004.