A survey on on-chip ESD protection in CMOS technology

Abstract

Nowadays, electrostatic discharge (ESD) protection is an important part of the fast I/O applications. In recent years, the number of ESD damages to ICs has considerably increased because of huge energy dissipation in an exceptionally small time in terms of the nanosecond. As the number of damages increase, the proposal of methods and designs for ESD protection by researchers has been increased subsequently. As this research area is undeveloped and still unexplored deeply, with this paper we intend to present a prearranged and broad outline of the study on ESD protection in Complementary Metal–Oxide–Semiconductor technology. This paper’s surveys present a review on on-chip ESD protection designed in favor of the applications of high-speed I/O using CMOS technology. The solutions to overcome different issues caused due to ESD are also discussed for on-chip ESD protection in Complementary Metal–Oxide–Semiconductor technology.