Implementation of Dual Stage Multi-rate Filter

Abstract

In this work, an effort is made towards the design and implementation of dual stage multi-rate digital filter architecture which is suitable for digital receivers and satellite applications with reduced VLSI cost function. The proposed dual stage decimation filter architecture consists of Higher Order Filter (HDF) as first section. To remove the droops created by the HDF section in the pass band and to get the smooth pass band frequency response characteristics, HDF filter is followed by a Corrector/Compensating Finite Impulse Response (FIR) filter network. The compensating FIR is designed using conventional Multiplier and Accumulator (MAC) unit. Initially, the filter architectures frequency response are obtained as per the given specifications using MATLAB. Then, Field Programmable Gate Array (FPGA) based performance metrics are captured and analyzed with respect to area, dynamic power dissipation, delay and power delay product. Based on the FPGA performance metrics, it is observed that the proposed dual stage filter leads to 22% of area saving and 9.5 % reduction in dynamic power dissipation. Mainly these filters are best suited for Digital Signal Processing applications in wireless receivers.