A novel two fold edge activated memory cell with low power dissipation and high speed

Abstract

In today’s increasing demand of higher integration levels in VLSI and ULSI circuits’ memory capacity and frequency of RAM is playing a major role in designing. Flip-flops are the micro cells for memories to store binary values. D flip-flops now days are used instead of any other because its designing is easy as far as area and power constraints are considered. So as to increase the bit rate of Flip-flop many triggering techniques were propose like single edge triggering and dual edge triggering. A novel D Flip-flop which uses only 14 transistors is explained using Two Fold Edge Triggering in this paper. From this paper we come to an understanding that at any temperature or at any supply voltage levels the proposed Flip-flop is efficient. Even though Power Delay product increases at lower voltage levels but still it is less compared to existing method. The input to output delay is greatly decreased as the number of transistors is reduced in dual data paths.