Electrical characteristics of double gate finfet under different modes of operation

Abstract

CMOS scaling has provided the enhancement of VLSI industry for its miniaturization of devices as well as increase in the operating speed at the expense of power dissipation. The three metrics of VLSI industry speed, area and power are interlinked to each other such that one metric has to be compromised for another metric to have better value depending on which particular application to be targeted. Furthur sclaing of cmos is not possible because of material and process technology limits. Because of second order effects prevailing in CMOS researchers are looking for alternative replacement for CMOS which overcomes the second order effects existing in CMOS scaling and provide very less power dissipation. Now a day’s power dissipation is very crucial parameter because of miniaturization of devices a feature called portability came in to picture where battery is essential requirement. The battery technology has not evolved as much as the VLSI technology as evolved over the years which has left no option for the designers to design the devices which consume less power and give more battery life which is the most primary requirement from customer point of view. In this regard FINFET is found to be one of the right substitute for CMOS to design the applications which are targeted to have low power delay product. FINFET electrical characteristics are plotted under different modes of operation and leakage currents are compared for N-Type and P-type FINFETs, and concluded that back gate biasing reduces leakage currents.