FPGA implementation of LDPC decoder

Abstract

Low-density parity-check (LDPC) codes are the most powerful error-correcting codes used in the transmission of signals and also provide a near-optimal performance that can approach to capacity for a lot of different channels. LDPC codes are preferred nowadays as it is bandwidth-efficient and provide less Bit Error Rate (BER). In this paper, LDPC decoder using log-belief propagation algorithm which reduces the complexity is implemented with Xilinx System Generator (XSG) blocks combined with Simulink blocks and finally dumped on Virtex-5 FPGA board for hardware, and device utilization summary was also found.