Implementation of low power and memory efficient 2D FIR filter architecture

Abstract

A memory efficient design is analyzed to derive a low power-area-delay two dimensional (2D) Finite Impulse Response (FIR) filter architecture. The parallel processing concept is introduced in the fully direct-form 2D FIR filter. Due to this, memory reuse is carried out, and it reduces the overall storage memory of the FIR filter. The non-separable 2D FIR filter structure is designed and implemented with block size L and filter length N. The high speed and power efficient multipliers and optimized Carry Look Ahead (CLA) adders are used in the arithmetic module of the FIR filter and a pipelined adder unit is used for the final computation of the filter output. The switch level modification in the logic gates is proposed to reduce the area, power and delay of the adders. This proposed architecture is represented in HDL code and validation is carried out in CADENCE environment using NC Simulator and RTL Compiler synthesis tool. The area, power and delay reports are generated and compared with existing memory efficient 2D FIR filter hardware structures. The power is reduced to 44% and delay is reduced by 20% using Modified CLA (MCLA) adders and pipelining in the design.