Low power, high speed and low area of fin FET 4:1multiplexer VLSI circuit design in 18nm technology

Abstract

In this paper, a Fin FET 4:1Multiplexer utilizing 24 transistors has been proposed. The proposed Fin FET 24T 4:1 Multiplexer is developed utilizing in Cadence 18 nm innovation. The proposed outcomes are contrasted and the prior real structure. We have diminished two transistors by utilizing Morgan's laws contrasted and the prior real plan. Customary of Fin FET 4:1 Multiplexer utilizing 26 transistors as far as power, postponement and zone. It is played out the Dynamic power is diminished by 47.77%, Leakage Power is diminished 29.09% and Static Power is diminished by 14.61%. It is likewise understood that the postponement is diminished by 94.13% and territory is diminished by 40.74% for 24 transistors Fin FET 4:1Multiplexer in Cadence 18nm Technology.