High performance FPGA implementation for SMS4

Abstract

SMS4 is an encryption algorithm supported in China WAPI standard. This paper implements the SMS4 algorithm for FPGA. We proposed iteration architecture and pipeline architecture respectively, utilizing the similarity between encryption and key-expansion to reduce area. The iteration architecture supports ECB/CBC mode, and throughput can achieve 721Mbps with cost of 1158 ALMs. The pipeline architecture can achieve 21760Mbit/s, using 7661 ALMs. Both of them can reach higher encryption and decryption throughput and lower area cost than implementations before. The functionality and performance are evaluated on Altera Straitx II FPGA device. © 2011 Springer-Verlag.