Reducing memory traffic via redundant store instructions

Abstract

Some memory writes have the particular behaviour of not modifying memory since the value they write is equal to the value before the write. These kind of stores are what we call Redundant Stores. In this paper we study the behaviour of these particular stores and show that a significant saving on memory traffic between the first and second level caches can be avoided by exploiting this feature. We show that with no additional hardware (just a simple comparator) and without increasing the cache latency, we can achieve on average a 10% of memory traffic reduction.