Analysis of the subthreshold CMOS logic inverter

Abstract

There is no doubt that operating the MOSFET transistor in the subthreshold region, where the power-supply voltage is less than the threshold voltage, has an increasing importance due to the reduced power consumption. In this paper, the analysis of the CMOS logic inverter in the subthreshold region is addressed quantitatively with the static and dynamic characteristics investigated and compared with that operating in the superthreshold region. Specifically, compact-form equations are derived for the output-low voltage, output-high voltage, maximum-input voltage at logic “0,” minimum-input voltage at logic “1,” and threshold voltage of the inverter. Also, the static-power consumption and dynamic-power consumption are investigated and equations are derived for them. Compact-form expressions are derived for the low-to-high and the high-to-low propagation delays along with the fan-out. Qualitative discussions are also provided. The results of the quantitative analysis are verified by comparison with the simulation results adopting the 65 nm CMOS technology.