Abstract
Globally Asynchronous Locally Synchronous (GALS) Systems have provoked renewed interest over recent years as they have the potential to combine the benefits of asynchronous and synchronous design paradigms. It has been applied to ASICs, but not yet applied to FPGAs. In this paper we propose applying GALS techniques to FPGAs in order to overcome the limitation on timing imposed by slow routing. © Springer-Verlag Berlin Heidelberg 2003.
Cite
CITATION STYLE
Royal, A., & Cheung, P. Y. K. (2003). Globally asynchronous locally synchronous FPGA architectures. Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2778, 355–364. https://doi.org/10.1007/978-3-540-45234-8_35
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