One-Sided Schmitt-Trigger-Based Low Power Read Decoupled 11T CNTFET SRAM with Improved Stability

Abstract

The power requirements of wireless sensor networks and internet of things (IoT) applications heavily rely on batteries. It is crucial that the memory cells utilized in these applications must consume low-power to prolong the battery life. In this paper, a static-random access memory (SRAM) cell is introduced that incorporates eleven carbon nanotube field-effect transistors (CNTFETs). The proposed 11T CNTFET SRAM cell employs a single-ended approach for reading and writing data and read-decoupled approach to access data in the bit cell. In addition to this, Schmitt-trigger (ST) inverter is incorporated within the bit cell, to enhance its stability and power efficiency. To evaluate the performance of the proposed 11T CNTFET SRAM cell, 32 nm CNTFET model developed by the Stanford University- and HSPICE simulation tool are used for the simulations. The proposed 11T CNTFET bit cell’s results show write power, hold power, read power, write static noise margin, hold static noise margin read static noise margin, write delay and read delay of 0.182 nW, 0.2 nW, 0.197 nW, 453.5 mV, 380.5 mV, 383.3 mV, 102 pS and 41.9 pS, respectively at VDD = 0.9 V. Comprehensive parametric simulations are also carried out to analyze the impact of various CNTFET parameters on performance metrics of proposed SRAM cell. The performance of proposed SRAM is fairly compared with existing SRAM cells implemented with CNTFETs and results are found to be quite encouraging. The proposed SRAM cell finds its suitability for use in designing memory devices targeted for wireless sensor networks, Internet of Things and smart biomedical gadgets.