A power-sum systolic architecture in GF(2m)

Abstract

Finite field arithmetic operations have been widely used in the areas of data communication and network security applications, and high-speed and low-complexity design for finite field arithmetic is very necessary for these applications. This paper presents a new algorithm and architecture for the power-sum operation (AB2+C) over GF(2m) using the standard basis among these finite field operations. The proposed algorithm is based on the MSB-first fashion, plus the architecture has a low hardware complexity and small latency compared to conventional approaches. In particular, the hardware complexity and latency of the proposed array are about 19.8% and 25% lower than Wei’s over GF(2m), respectively. In addition, since the proposed architecture incorporates simplicity, regularity, modularity, and pipelinability, it is well suited to VLSI implementation and can be easily applied to inversion architecture.