NoC (Network-on-Chip) is inherently suitable to the dynamic partial reconfiguration. DRNoC, combining these two promising technologies, will be a desirable platform for the next generation portable eletronic consuming products. Taking the irregular 2D mesh NoC as a study case, this paper discusses the design methodology of DRNoC, including the topology, router, mapping algorithm, routing algorithm, implementation and simulation of DRNoC. © 2011 Springer-Verlag Berlin Heidelberg.
CITATION STYLE
Gu, H. (2011). Design methodology of dynamically reconfigurable network-on-chip. In Lecture Notes in Electrical Engineering (Vol. 100 LNEE, pp. 111–116). https://doi.org/10.1007/978-3-642-21762-3_14
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