Performance Analysis of Dual Edge Triggered Memory Cells using Multiple C-Elements

Abstract

This research paper presents a low conditional discharge(C-element) Flip-Flops that are basic elements in all digital design. The existing circuits are power hunger due to the dynamic and static power dissipation increases. For reducing power consumption C element technique is used to reduce glitches at the data out. Results obtained through 130nm technology shows reduction in energy dissipation and delay. Average dynamic power dissipation of the proposed flip-flop is compare with two existing techniques. Average power of proposed flip-flop is reduced by 28.41% and 36.18% when compared with Latch-Mux flip-flop and Latch-Mux using C-element.