Physical Design of a Multibit D FlipFlop-Based Linear Feedback Shift Register

Abstract

In the emerging world of VLSI technologies, the challenges for the VLSI designers keep raising to produce circuits that consume low power, area and speed. The Linear Feedback Shift Register (LFSR) can be employed to generate pseudorandom patterns in test generators. The standard implementation of LFSR uses D flipflops and exclusive OR connected linearly. The proposed technique uses multibit flipflops for designing the LFSR. Multibit flipflop is used in applications where low power and area is the main concern. The total design area is reduced due to the usage of the multibit flipflop without affecting the performance of the design. The proposed design simulation is done using the Xilinx IDE. The synthesis and physical design are carried out using Cadence Genus and Innovus tools. The result analysis provides that the power of standard eight-bit LFSR is about 92,732.236 nW, and it is reduced to 35,217.804 nW as we use multibit flipflops to implement an eight-bit LFSR. The chip area is also reduced as it uses only four multibit flipflops in place of an eight D flipflop in the proposed design.