Design of Low-Power Parallel Prefix Adder Templates Using Asynchronous Techniques

Abstract

This paper aims to design low-power circuits like an adder, buffer, AOI, and logic gates using asynchronous quasi delay insensitive (QDI) templates, essential for many arithmetic computations. Adder is a fundamental building block for applications like ALU, microprocessors, and digital signal processors. The present trendy parallel prefix adder KSA is modeled and verified with various asynchronous QDI templates. The prominent templates include pre-charged half buffer, autonomous signal validity half buffer, and sense amplifier half buffer in dual-rail encoding style. Due to clock circuitry, synchronous circuits determine more switching activity, which dissipates more power. This drawback is overcome through clock-less circuits, which dissipate less power by reducing the switching activity without degrading the functionality of a circuit. An asynchronous circuit has various timing approaches such as QDI, delay insensitive, and bundled data. Still, the QDI approach has significant advantages in power dissipation, delay, and energy savings. The major drawback of QDI templates is the completion detector block, which dissipates more power and occupies a large area overhead. To overcome this drawback, an advanced QDI template—sense amplifier half buffer is designed to provide low power, less delay with efficient energy due to the utilization of sub-threshold process and controlled reset transistor in evaluation block and the absence of completion detector circuit. The paper describes the performance aspects of 32-bit KSA using various QDI templates in terms of multiple metrics like power, delay, and energy using the mentor graphics EDA tool.